1. Field of the Invention
The present invention relates to a delay circuit used in a semiconductor device, and more particularly to a shared delay circuit of a semiconductor device which can share a plurality of delay elements having the same function by integrating the delay elements.
2. Description of the Prior Art
As generally known in the art, a semiconductor device has diverse kinds of delay circuits installed therein for the purpose of a buffer function, time delay, etc. Accordingly, in many cases, a plurality of delay circuits having the same time delay are provided in a semiconductor device.
FIG. 1 is a view illustrating the construction of a related art delay circuit which receives input signals and then outputs the signals after delaying them for a predetermined time. For reference, the respective delay circuits have the same delay time and the same function.
In FIG. 1, the reference numeral “PERI” denotes a peripheral area which provides input signals INPUT 0, INPUT 1, INPUT 2, and INPUT 3 to a circuit block, and “DELAY” denotes a delay circuit. Also, “BLOCK” denotes a circuit block having the same function in the semiconductor device.
FIG. 1 shows a case that the number of circuit blocks is 4, and the input signals INPUT 0, INPUT 1, INPUT 2, and INPUT 3 are inputted to respective circuit blocks BLOCK 0, BLOCK 1, BLOCK2 and BLOCK3, respectively.
In operation, the selection of the respective input signals and the circuit blocks is typically performed by a control signal (for example, address signal). In the case that an input signal corresponding to a specified circuit block is applied by the control signal, the input signal causes an output signal OUTPUT to be produced through a delay circuit in the circuit block, and this output signal is used in the corresponding circuit block. Generally, one of the input signals INPUT 0, INPUT 1, INPUT 2, and INPUT 3 is selected, but in a special case, two or more input signals may be simultaneously selected.
FIGS. 2A and 2B are views illustrating a signal flow of delay signals obtained by delaying the input signals for a predetermined time using the related art delay circuit illustrated in FIG. 1. Specifically, FIG. 2A illustrates a delay process of a level signal applied in the form of a high/low level, and FIG. 2B illustrates a delay process of a pulse signal. As illustrated, it can be recognized that the level signal or the pulse signal applied to the delay circuit is outputted, being delayed for a predetermined time.
In the related art, if there is a plurality of circuit blocks having the same function as shown in FIG. 1, it is general that the input signals INPUT 0, INPUT 1, INPUT 2, and INPUT 3 inputted to the respective circuit blocks pass through a plurality of separated paths even though they are signals for the same operation.
In this case, the delay circuits, which have the same constituent elements, i.e., a resistor and a capacitor, and which have the same time delay, are arranged in a repeated form for each circuit block, and this causes the area efficiency to deteriorate. Also, since the delay circuits are separately arranged in different locations, they may present different time delay characteristics due to a change of process, voltage and temperature.